1. Field of the Invention
This invention is directed to a method of manufacturing a semiconductor structure. More particularly, this invention is directed to a method of manufacturing a semiconductor structure to obtain a structure comprising a Si base, at least one insulating layer residing on the Si base, and a SiC layer residing on the insulating layer, in which the SiC layer is non-indigenous to the Si base. The semiconductor structure may be employed, for example, in the fabrication of high temperature instrumentation such as high temperature electronics and sensors for use in environments such as aircraft engines.
2. Background Information
The use of layers of semiconductor materials in the manufacture of sensing elements such as pressure sensors is well known to those skilled in the art. Such sensing elements are typically fabricated from one or more thin semiconductor layers residing on a thick support structure. The thin semiconductor layer or layers may be obtained by bonding the semiconductor material to a support wafer (e.g. a Si wafer), with an intermediate insulating layer residing therebetween. The semiconductor material is then thinned, typically via etching or grinding, to the desired thickness.
For high temperature sensor applications semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and diamond are of particular interest, due to the wide band gap of such materials. More particularly, as disclosed, for example, in U.S. Pat. No. 5,798,293 (Harris), the cubic form 3C polytype of single crystal SiC (3Cxe2x80x94SiC) is an advantageous semiconductor material. However, such materials are typically difficult to process, as they tend to be hard, brittle, fragile and chemically resistant. In particular, although SiC is a preferred material for use in high temperature sensor applications, SiC is very hard and chemically resistant, which makes fabrication of the sensing element difficult. For example, bonding of SiC wafers requires flat and smooth wafer surfaces, yet polishing SiC surfaces to achieve sufficient flatness and surface finish is difficult due to the hardness of SiC. Moreover, even if bonding of the SiC surface is accomplished, thinning of the SiC layer via conventional grinding or a combination of chemical and mechanical etching or polishing remains difficult.
Various other techniques are known for fabricating desired composite semiconductor material structures. For example, a thin film of active material (e.g. Si or SiC) may be placed on a xe2x80x9chandlexe2x80x9d wafer. Thereafter, insulating layers may be applied to both the active material thin layer and a separate xe2x80x9cbasexe2x80x9d wafer. The insulating layers are then bonded or annealed to form a single structure, and the xe2x80x9chandlexe2x80x9d wafer is removed via etching, grinding or polishing or a combination thereof to yield a structure having a base wafer, an active top layer, and an insulating layer therebetween.
However, because of the disadvantages of etching, grinding and polishing techniques to remove excess Si material (such as the xe2x80x9chandlexe2x80x9d wafer), other semiconductor material fabrication methods have been developed. For example, in the so-called xe2x80x9cSMART-CUTxe2x80x9d process, described in U.S. Pat. No. 5,374,564 (Bruel), which is incorporated herein by reference, a thin semiconductor material film is prepared by bombarding a face of a semiconductor wafer material (e.g. a monocrystalline Si wafer) with hydrogen ions to a depth close to the average penetration depth of ions into the wafer, thereby defining an upper wafer portion (i.e. a thin film) and a lower wafer portion (i.e. the substrate). A stiffener constituting at least one rigid material layer is brought into contact with the planar face of the thin film portion of the wafer, and the wafer-stiffener assembly is thereafter thermally treated, thereby causing separation of the thin film from the substrate by the formation and coalescence of hydrogen filled microcracks.
Similarly, a method of fabricating a 3Cxe2x80x94SiC semiconductor layer on a SiO2 insulating layer is described by K. Vinod et al. in xe2x80x9cFabrication of Low Defect Density 3Cxe2x80x94SiC on SiO2 Structures Using Wafer Bonding Techniques,xe2x80x9d J. of Electronic Materials, Vol. 27, pp. L17-20 (1998) (referred to herein as Vinod et al.), which is incorporated herein by reference. The paper describes the fabrication of a 3Cxe2x80x94SiC on SiO2 structure in which etching is employed to expose a SiC surface on an SiO2 layer.
In view of the above-described problems associated with the use of grinding, polishing and etching techniques to obtain the desired SiC active layer, it would be desirable to employ a method of manufacturing semiconductor structures having a SiC active layer residing on an insulating layer which avoids the use of such techniques.
It is one object of this invention to provide a method of preparing a semiconductor structure having a SiC active layer residing on an insulating layer which is prepared by using a handle wafer which is removed without etching, grinding or polishing. It is yet another object of this invention to provide high temperature pressure sensors, high temperature sensors and integrated electronics prepared from the semiconductor structure of this invention, as well as a method of preparing such sensors and integrated electronics.
It is one feature of this invention that a handle wafer is prepared having a Si substrate, at least one SiC active layer applied to the substrate, and an insulating layer applied to the SiC active layer. The handle wafer is bombarded with ions and the ions are implanted to a desired depth within the SiC active layer. At least one base wafer having an insulating layer is also provided, and the insulating layers of the handle and base wafers are bonded, thereby forming a single structure. Upon thermal treatment of the structure as described in the xe2x80x9cSMART-CUTxe2x80x9d process as described in U.S. Pat. No. 5,374,564 (Bruel), the Si substrate and a portion of each SiC layer of the handle wafer is removed, yielding at least one semiconductor structure having a base wafer, an oxide insulating layer residing on the base wafer, and a top SiC active layer residing on the insulating layer.
The method of this invention advantageously may employ thicker wafers which tend to remain flat and facilitate bonding thereto. In addition, the method of this invention advantageously permits the manufacture of large diameter (say 4 inches in diameter) SiC on insulator (SiCOI) having excellent crystal properties which are obtained without using etching. Other objects, features and advantages of this invention will be apparent to those skilled in the art in view of the detailed description of the invention provided below.
The method of this invention comprises:
providing a first material comprising (i) a first (i.e. handle) wafer comprising silicon, (ii) at least one SiC conversion layer obtained by converting a portion of the silicon from the handle wafer to SiC, (iii) at least one layer of non-indigenous SiC applied to the conversion layer, and (iv) at least one oxide layer applied to the non-indigenous SiC layer, wherein a region of the non-indigenous SiC layer has ions implanted therein, thereby establishing an implant region therein which defines a first portion of the non-indigenous SiC layer and a second portion of the non-indigenous SiC layer;
providing at least one additional material comprising (i) a second (i.e. base wafer) comprising silicon, and (ii) an oxide layer applied to a face of the base wafer;
bonding the oxide layer of the first material and oxide layer of the additional material to provide an assembly of the first material and additional material; and
separating at the implant region the second portion of the non-indigenous SiC layer from the first portion of the non-indigenous SiC layer, thereby providing at least one semiconductor structure having a silicon base, at least one oxide insulating layer thereon, and a non-indigenous SiC active top layer residing on the oxide insulating layer. The semiconductor structure obtained from the method of this invention may be used to fabricate integrated electronics, temperature sensors, pressure sensors or other instrumentation which may be used in high temperature environments such as aircraft engines.